SH7211 Datasheet, PDF (311/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
Table 8.16 Conditions for Determining Number of Idle Cycles
No. Condition
Description
Range Note
(1) DMAIW[2:0] in These bits specify the number of 0 to 12 When 0 is specified for the
CMNCR
idle cycles for DMA single address
number of idle cycles, the
transfer. This condition is effective
DACK signal may be asserted
only for single address transfer and
continuously. This causes a
generates idle cycles after the
discrepancy between the
access is completed.
number of cycles detected by
the device with DACK and the
DMAC transfer count,
resulting in a malfunction.
(2) IW***[2:0] in
CSnBCR
These bits specify the number of 0 to 12
idle cycles for access other than
single address transfer. The
number of idle cycles can be
specified independently for each
combination of the previous and
next cycles. For example, in the
case where reading CS1 space
followed by reading other CS
space, the bits IWRRD[2:0] in
CS1BCR should be set to B'100 to
specify six or more idle cycles. This
condition is effective only for access
cycles other than single address
transfer and generates idle cycles
after the access is completed.
Do not set 0 for the number of
idle cycles between memory
types which are not allowed
to be accessed successively.
(3) SDRAM-related These bits specify precharge
0 to 3
bits in
completion and startup wait cycles
CSnWCR
and idle cycles between commands
for SDRAM access. This condition
is effective only for SDRAM access
and generates idle cycles after the
access is completed
Specify these bits in
accordance with the
specification of the target
SDRAM.
(4) WM in
CSnWCR
This bit enables or disables external 0 or 1
WAIT pin input for the memory
types other than SDRAM. When
this bit is cleared to 0 (external
WAIT enabled), one idle cycle is
inserted to check the external WAIT
pin input after the access is
completed. When this bit is set to 1
(disabled), no idle cycle is
generated.
Rev. 2.00 May. 08, 2008 Page 287 of 1200
REJ09B0344-0200