SH7211 Datasheet, PDF (213/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
Bit
18 to 16
Bit Name
IWRRS[2:0]
Initial
Value
011
15
⎯
0
14 to 12 TYPE[2:0] 000
11
ENDIAN
0
R/W Description
R/W Idle Cycles for Read-Read in the Same Space
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target cycle is a read-read cycle of which
continuous access cycles are for the same space.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Specify the type of memory connected to a space.
000: Normal space
001: Burst ROM (clock asynchronous)
010: MPX-I/O
011: SRAM with byte selection
100: SDRAM
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Burst ROM (clock synchronous)
For details of memory type in each area, see tables 8.2
and 8.3.
R/W Endian Select
Specifies data alignment in a space.
0: Big endian
1: Little endian
Rev. 2.00 May. 08, 2008 Page 189 of 1200
REJ09B0344-0200