SH7211 Datasheet, PDF (425/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
0
CMFW5
0
R/(W)*¹ Compare Match/Input Capture Flag W5
Status flag that indicates the occurrence of TGRW_5
input capture or compare match. Only 0 can be written to
clear this flag.
[Clearing condition]
• When 0 is written to CMFW5 after reading CMFW5 =
1
[Setting conditions]
• When TCNTW_5 = TGRW_5 and TGRW_5 is
functioning as output compare register
• When TCNTW_5 value is transferred to TGRW_5 by
input capture signal and TGRW_5 is functioning as
input capture register
• When TCNTW_5 value is transferred to TGRW_5 and
TGRW_5 is functioning as a register for measuring
the pulse width of the external input signal. *²
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Timing for transfer is set by the IOC bit in the timer I/O control register U_5/V_5/W_5
(TIORU_5/V_5/W_5).
10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)
The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring
data from the buffer register to the timer general register in PWM mode. The MTU2 has three
TBTM registers, one each for channels 0, 3, and 4.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
- TTSE TTSB TTSA
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W
Rev. 2.00 May. 08, 2008 Page 401 of 1200
REJ09B0344-0200