SH7211 Datasheet, PDF (929/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
21.4.3 Programming/Erasing Interface Parameters
The programming/erasing interface parameters specify the operating frequency, user branch
destination address, storage place for program data, programming destination address, and erase
block and exchanges the processing result for the downloaded on-chip program. This parameter
uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value
is undefined.
At download all CPU registers are stored, and at initialization or when the on-chip program is
executed, CPU registers except for R0 are stored. The return value of the processing result is
written in R0. Since the stack area is used for storing the registers or as a work area, the stack area
must be saved at the processing start. (The maximum size of a stack area to be used is 128 bytes.)
The programming/erasing interface parameters are used in the following four items.
1. Download control
2. Initialization before programming or erasing
3. Programming
4. Erasing
These items use different parameters. The correspondence table is shown in table 21.6.
The processing results of initialization, programming, and erasing are returned, but the bit contents
have different meanings according to the processing program. See the description of FPFR for
each processing.
Rev. 2.00 May. 08, 2008 Page 905 of 1200
REJ09B0344-0200