SH7211 Datasheet, PDF (797/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 17 A/D Converter (ADC)
17.3.1 A/D Control Register (ADCR)
ADCR is an 8-bit readable/writable register that selects A/D conversion mode and others.
Bit: 7
6
5
4
3
ADST ADCS ACE ADIE -
Initial value: 0
0
0
0
0
R/W: R/W R/W R/W R/W R
2
1
0
- TRGE EXTRG
0
0
0
R R/W R/W
Initial
Bit Bit Name Value
7 ADST
0
6 ADCS
0
5 ACE
0
R/W Description
R/W A/D Start
When this bit is cleared to 0, A/D conversion is stopped
and the A/D converter enters the idle state. When this bit
is set to 1, A/D conversion is started. In single-cycle scan
mode, this bit is automatically cleared to 0 when A/D
conversion ends on the selected single channel. In
continuous scan mode, A/D conversion is continuously
performed for the selected channels in sequence until this
bit is cleared by software, a reset, or in software standby
mode, or module standby mode.
R/W A/D Continuous Scan
Selects either a single-cycle or a continuous scan in scan
mode. This bit is valid only when scan mode is selected.
0: Single-cycle scan
1: Continuous scan
When changing the operating mode, first clear the ADST
bit to 0.
R/W Automatic Clear Enable
Enables or disables the automatic clearing of ADDR after
ADDR is read by the CPU or DMAC. When this bit is set
to 1, ADDR is automatically cleared to H'0000 after the
CPU or DMAC reads ADDR. This function allows the
detection of any renewal failures of ADDR.
0: Automatic clearing of ADDR after being read is
disabled.
1: Automatic clearing of ADDR after being read is enabled.
Rev. 2.00 May. 08, 2008 Page 773 of 1200
REJ09B0344-0200