SH7211 Datasheet, PDF (971/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
(2) User Branch Processing Intervals
The intervals for executing the user branch processing differs in programming and erasing. The
processing phase also differs. Table 21.10 lists the maximum intervals for initiating the user
branch processing when the CPU clock frequency is 40 MHz.
Table 21.10 Initiation Intervals of User Branch Processing
Processing Name
Maximum Interval
Programming
Approximately 2 ms*
Erasing
Approximately 15 ms*
Note: * Reference value
However, when operation is done with CPU clock of 40 MHz, maximum values of the time until
first user branch processing are as shown in table 21.11.
Table 21.11 Initial User Branch Processing Time
Processing Name
Maximum
Programming
Approximately 2 ms*
Erasing
Approximately 15 ms*
Note: * Reference value
(3) Write to Flash-Memory Related Registers by DMAC
While an instruction in on-chip RAM is being executed, the DMAC can write to the SCO bit in
FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure
that these registers are not accidentally written to, otherwise an on-chip program may be
downloaded and destroy RAM or a MAT switchover may occur and the CPU get out of control.
(4) State in which Interrupts are Ignored
In the following modes or period, interrupt requests are ignored; they are not executed and the
interrupt sources are not retained.
• Boot mode
• Programmer mode
Rev. 2.00 May. 08, 2008 Page 947 of 1200
REJ09B0344-0200