SH7211 Datasheet, PDF (102/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 5 Exception Handling
Type
Exception Handling
Priority
Interrupt On-chip peripheral modules Multi-function timer pulse unit 2S (MTU2S) High
Port output enable 2 (POE2): OEI3
interrupt
I²C bus interface 3 (IIC3)
Serial communication interface with FIFO
(SCIF)
Instruction Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Slot illegal instructions (undefined code placed directly after a delayed
branch instruction*¹, instructions that rewrite the PC*², 32-bit
instructions*³, RESBANK instruction, DIVS instruction, and DIVU
instruction)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.
3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.
Rev. 2.00 May. 08, 2008 Page 78 of 1200
REJ09B0344-0200