SH7211 Datasheet, PDF (208/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
Bit
8 to 6
5
4
Bit Name
Initial
Value
DMAIW[2:0] 000
DMAIWA 0
⎯
1
R/W Description
R/W Wait states between access cycles when DMA single
address transfer is performed.
Specify the number of idle cycles to be inserted after
an access to an external device with DACK when DMA
single address transfer is performed. The method of
inserting idle cycles depends on the contents of
DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
R/W Method of inserting wait states between access cycles
when DMA single address transfer is performed.
Specifies the method of inserting the idle cycles
specified by the DMAIW[2:0] bit. Clearing this bit will
make this LSI insert the idle cycles when another
device, which includes this LSI, drives the data bus
after an external device with DACK drove it. However,
when the external device with DACK drives the data
bus continuously, idle cycles are not inserted. Setting
this bit will make this LSI insert the idle cycles after an
access to an external device with DACK, even when
the continuous access cycles to an external device
with DACK are performed.
0: Idle cycles inserted when another device drives the
data bus after an external device with DACK drove
it.
1: Idle cycles always inserted after an access to an
external device with DACK
R
Reserved
This bit is always read as 1. The write value should
always be 1.
Rev. 2.00 May. 08, 2008 Page 184 of 1200
REJ09B0344-0200