SH7211 Datasheet, PDF (1003/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Table 21.15 Error Codes
Code
H'00
H'11
H'21
H'22
H'24
H'25
H'26
H'27
H'29
H'2A
H'2B
H'51
H'52
H'53
H'54
H'80
H'FF
Description
No error
Sum check error
Non-matching device code error
Non-matching clock mode error
Bit-rate selection failure
Input frequency error
Frequency multiplier error
Operating frequency error
Block number error
Address error
Data length error (size error)
Erasure error
Non-erased error
Programming error
Selection processing error
Command error
Bit-rate matching acknowledge error
Section 21 Flash Memory
21.8.2 Areas for Storage of the Procedural Program and Data for Programming
In the descriptions in the previous section, storable areas for the programming/erasing procedure
programs and program data are assumed to be in on-chip RAM. However, the procedure programs
and data can be stored in and executed from other areas (e.g. external address space) as long as the
following conditions are satisfied.
1. The on-chip programming/erasing program is downloaded from the address set by FTDAR in
on-chip RAM, therefore, this area is not available for use.
2. The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure
this area is reserved.
3. Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be
executed in on-chip RAM.
4. The flash memory is accessible until the start of programming or erasing, that is, until the
result of downloading has been decided.
Rev. 2.00 May. 08, 2008 Page 979 of 1200
REJ09B0344-0200