SH7211 Datasheet, PDF (636/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
12.3 Register Descriptions
The POE2 has the following registers.
All these registers are initialized by a power-on reset, but are not initialized by a manual reset or in
sleep mode, software standby mode, or module standby mode.
Table 12.3 Register Configuration
Register Name
Input level control/status register 1
Output level control/status register 1
Input level control/status register 2
Output level control/status register 2
Input level control/status register 3
Software port output enable register
Port output enable control register 1
Port output enable control register 2
Abbreviation
ICSR1
OCSR1
ICSR2
OCSR2
ICSR3
SPOER
POECR1
POECR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
H'0000
H'0000
H'0000
H'0000
H'0000
H'00
H'00
H'7700
Address
H'FFFE5000
H'FFFE5002
H'FFFE5004
H'FFFE5006
H'FFFE5008
H'FFFE500A
H'FFFE500B
H'FFFE500C
Access
Size
16
16
16
16
16
8
8
16
Rev. 2.00 May. 08, 2008 Page 612 of 1200
REJ09B0344-0200