SH7211 Datasheet, PDF (656/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
(2) Low-Level Detection
Figure 12.3 shows the low-level detection operation. Sixteen continuous low levels are sampled
with the sampling clock selected by ICSR1 to ICSR3. If even one high level is detected during this
interval, the low level is not accepted.
The timing when the high-current pins enter the high-impedance state after the sampling clock is
input is the same in both falling-edge detection and in low-level detection.
Pφ
Sampling
clock
POE input
PB18/TIOC3B
When low level is
sampled at all points
When high level is
sampled at least once
8/16/128 clock
cycles
(1)
(2)
(1)
(2)
High-impedance state*
(3)
(16)
Flag set
(POE received)
(13) Flag not set
Note: * The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing.
Figure 12.3 Low-Level Detection Operation
12.4.2 Output-Level Compare Operation
Figure 12.4 shows an example of the output-level compare operation for the combination of
TIOC3B and TIOC3D. The operation is the same for the other pin combinations.
Pφ
PB18/
TIOC3B
PB19/
TIOC3D
Low level overlapping detected
High impedance state
Figure 12.4 Output-Level Compare Operation
Rev. 2.00 May. 08, 2008 Page 632 of 1200
REJ09B0344-0200