SH7211 Datasheet, PDF (64/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 2 CPU
2.4.2 Data Transfer Instructions
Table 2.11 Data Transfer Instructions
Instruction
MOV
#imm,Rn
MOV.W @(disp,PC),Rn
MOV.L @(disp,PC),Rn
MOV
Rm,Rn
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L Rm,@Rn
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L @Rm,Rn
MOV.B Rm,@-Rn
MOV.W Rm,@-Rn
MOV.L Rm,@-Rn
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
MOV.B R0,@(disp,Rn)
MOV.W R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.B @(disp,Rm),R0
MOV.W @(disp,Rm),R0
MOV.L
MOV.B
@(disp,Rm),Rn
Rm,@(R0,Rn)
Instruction Code
Operation
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
1110nnnniiiiiiii imm → sign extension → Rn 1
⎯ Yes Yes Yes
1001nnnndddddddd (disp × 2 + PC) → sign
extension → Rn
1
⎯ Yes Yes Yes
1101nnnndddddddd (disp × 4 + PC) → Rn
1
⎯ Yes Yes Yes
0110nnnnmmmm0011 Rm → Rn
1
⎯ Yes Yes Yes
0010nnnnmmmm0000 Rm → (Rn)
1
⎯ Yes Yes Yes
0010nnnnmmmm0001 Rm → (Rn)
1
⎯ Yes Yes Yes
0010nnnnmmmm0010 Rm → (Rn)
1
⎯ Yes Yes Yes
0110nnnnmmmm0000 (Rm) → sign extension → Rn 1
⎯ Yes Yes Yes
0110nnnnmmmm0001 (Rm) → sign extension → Rn 1
⎯ Yes Yes Yes
0110nnnnmmmm0010 (Rm) → Rn
1
⎯ Yes Yes Yes
0010nnnnmmmm0100 Rn-1 → Rn, Rm → (Rn)
1
⎯ Yes Yes Yes
0010nnnnmmmm0101 Rn-2 → Rn, Rm → (Rn)
1
⎯ Yes Yes Yes
0010nnnnmmmm0110 Rn-4 → Rn, Rm → (Rn)
1
⎯ Yes Yes Yes
0110nnnnmmmm0100 (Rm) → sign extension → Rn, 1
Rm + 1 → Rm
⎯ Yes Yes Yes
0110nnnnmmmm0101 (Rm) → sign extension → Rn, 1
Rm + 2 → Rm
⎯ Yes Yes Yes
0110nnnnmmmm0110 (Rm) → Rn, Rm + 4 → Rm 1
⎯ Yes Yes Yes
10000000nnnndddd R0 → (disp + Rn)
1
⎯ Yes Yes Yes
10000001nnnndddd R0 → (disp × 2 + Rn)
1
⎯ Yes Yes Yes
0001nnnnmmmmdddd Rm → (disp × 4 + Rn)
1
⎯ Yes Yes Yes
10000100mmmmdddd (disp + Rm) → sign extension 1
→ R0
⎯ Yes Yes Yes
10000101mmmmdddd (disp × 2 + Rm) →
sign extension → R0
1
⎯ Yes Yes Yes
0101nnnnmmmmdddd (disp × 4 + Rm) → Rn
1
⎯ Yes Yes Yes
0000nnnnmmmm0100 Rm → (R0 + Rn)
1
⎯ Yes Yes Yes
Rev. 2.00 May. 08, 2008 Page 40 of 1200
REJ09B0344-0200