SH7211 Datasheet, PDF (969/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
CPU cycle
CPU operation for instruction
that sets SCO bit to 1
Interrupt acceptance
n
Fetch
n+1
Decoding
(a)
n+2
Execution
n+3
Execution
(b)
n+4
Execution
(a) When the interrupt is accepted at the (n + 1) cycle or before
After the interrupt processing completes, the SCO bit is set to 1 and download is executed.
(b) When the interrupt is accepted at the (n + 2) cycle or later
The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated.
Figure 21.18 Timing of Contention between SCO Download Request and Interrupt Request
2. Generation of interrupt requests during downloading
Ensure that interrupts are not generated during downloading that is initiated by the SCO bit.
Rev. 2.00 May. 08, 2008 Page 945 of 1200
REJ09B0344-0200