SH7211 Datasheet, PDF (168/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 7 User Break Controller (UBC)
Figure 7.1 shows a block diagram of the UBC.
Access
control
I bus
IAB
C bus
MAB FAB
Access
comparator
Address
comparator
Channel 0
BBR_0
BAR_0
BAMR_0
I bus
Access
comparator
Address
comparator
Channel 1
BBR_1
BAR_1
BAMR_1
Access
comparator
Address
comparator
Channel 2
BBR_2
BAR_2
BAMR_2
Access
comparator
Address
comparator
Channel 3
BBR_3
BAR_3
BAMR_3
[Legend]
BBR: Break bus cycle register
BAR: Break address register
BAMR: Break address mask register
BRCR: Break control register
Control
BRCR
User break interrupt request
UBCTRG pin output
Figure 7.1 Block Diagram of UBC
Rev. 2.00 May. 08, 2008 Page 144 of 1200
REJ09B0344-0200