SH7211 Datasheet, PDF (16/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

10.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ...... 558
10.7.13 Counter Value during Complementary PWM Mode Stop .................................... 560
10.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 560
10.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 561
10.7.16 Overflow Flags in Reset Synchronous PWM Mode ............................................. 562
10.7.17 Contention between Overflow/Underflow and Counter Clearing......................... 563
10.7.18 Contention between TCNT Write and Overflow/Underflow................................ 564
10.7.19 Cautions on Transition from Normal Operation or PWM Mode 1
to Reset-Synchronized PWM Mode ..................................................................... 564
10.7.20 Output Level in Complementary PWM Mode
and Reset-Synchronized PWM Mode................................................................... 565
10.7.21 Interrupts in Module Standby Mode ..................................................................... 565
10.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection............ 565
10.8 MTU2 Output Pin Initialization......................................................................................... 566
10.8.1 Operating Modes .................................................................................................. 566
10.8.2 Reset Start Operation ............................................................................................ 566
10.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. ................. 567
10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error
during Operation, etc. ........................................................................................... 568
Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) ................................599
11.1 Input/Output Pins............................................................................................................... 603
11.2 Register Descriptions ......................................................................................................... 604
Section 12 Port Output Enable 2 (POE2) ............................................................607
12.1 Features.............................................................................................................................. 608
12.2 Input/Output Pins............................................................................................................... 610
12.3 Register Descriptions ......................................................................................................... 612
12.3.1 Input Level Control/Status Register 1 (ICSR1) .................................................... 613
12.3.2 Output Level Control/Status Register 1 (OCSR1) ................................................ 617
12.3.3 Input Level Control/Status Register 2 (ICSR2) .................................................... 618
12.3.4 Output Level Control/Status Register 2 (OCSR2) ................................................ 621
12.3.5 Input Level Control/Status Register 3 (ICSR3) .................................................... 622
12.3.6 Software Port Output Enable Register (SPOER) .................................................. 624
12.3.7 Port Output Enable Control Register 1 (POECR1)............................................... 626
12.3.8 Port Output Enable Control Register 2 (POECR2)............................................... 627
12.4 Operation ........................................................................................................................... 630
12.4.1 Input Level Detection Operation .......................................................................... 631
12.4.2 Output-Level Compare Operation ........................................................................ 632
12.4.3 Release from High-Impedance State .................................................................... 633
Rev. 2.00 May. 08, 2008 Page xvi of xxiv
REJ09B0344-0200