SH7211 Datasheet, PDF (439/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.3.17 Timer Counter Synchronous Start Register (TCSYSTR)
TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 and
MTU2S counters. Note that the MTU2S does not have TCSYSTR.
Bit: 7
6
5
4
3
2
1
0
SCH0 SCH1 SCH2 SCH3 SCH4 - SCH3S SCH4S
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R/(W)* R/(W)*
Note: * Only 1 can be written to set the register.
Initial
Bit
Bit Name Value R/W Description
7
SCH0
0
R/(W)* Synchronous Start
Controls synchronous start of TCNT_0 in the MTU2.
0: Does not specify synchronous start for TCNT_0 in
the MTU2
1: Specifies synchronous start for TCNT_0 in the MTU2
[Clearing condition]
• When 1 is set to the CST0 bit of TSTR in MTU2
while SCH0 = 1
6
SCH1
0
R/(W)* Synchronous Start
Controls synchronous start of TCNT_1 in the MTU2.
0: Does not specify synchronous start for TCNT_1 in
the MTU2
1: Specifies synchronous start for TCNT_1 in the MTU2
[Clearing condition]
• When 1 is set to the CST1 bit of TSTR in MTU2
while SCH1 = 1
Rev. 2.00 May. 08, 2008 Page 415 of 1200
REJ09B0344-0200