SH7211 Datasheet, PDF (324/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
• Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND
can be set independently.
• Support of reload functions in DMA transfer information registers: DMA transfer using the
same information as the current transfer can be repeated automatically without specifying the
information again. Modifying the reload registers during DMA transfer enables next DMA
transfer to be done using different transfer information. The reload function can be enabled or
disabled independently in each channel.
Rev. 2.00 May. 08, 2008 Page 300 of 1200
REJ09B0344-0200