SH7211 Datasheet, PDF (182/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 7 User Break Controller (UBC)
7.3.10 Break Address Register_3 (BAR_3)
BAR_3 is a 32-bit readable/writable register. BAR_3 specifies the address used as a break
condition in channel 3. The control bits CD3_1 and CD3_0 in the break bus cycle register_3
(BBR_3) select one of the three address buses for a break condition of channel 3. BAR_3 is
initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or
in software standby mode or sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BA3_31 BA3_30 BA3_29 BA3_28 BA3_27 BA3_26 BA3_25 BA3_24 BA3_23 BA3_22 BA3_21 BA3_20 BA3_19 BA3_18 BA3_17 BA3_16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BA3_15BA3_14BA3_13BA3_12BA3_11BA3_10 BA3_9 BA3_8 BA3_7 BA3_6 BA3_5 BA3_4 BA3_3 BA3_2 BA3_1 BA3_0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 BA3_31 to All 0
BA3_0
R/W Break Address 3
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions of channel 3.
When the C bus and instruction fetch cycle are
selected by BBR_3, specify an FAB address in bits
BA3_31 to BA3_0.
When the C bus and data access cycle are selected by
BBR_3, specify an MAB address in bits BA3_31 to
BA3_0.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_3 to 0.
Rev. 2.00 May. 08, 2008 Page 158 of 1200
REJ09B0344-0200