SH7211 Datasheet, PDF (808/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 17 A/D Converter (ADC)
A/D conversion execution
ADST
ADST set
ADST cleared*
ADF
AN0
Waiting for
conversion
S
AN1
Waiting for
conversion
AN2
Waiting for
conversion
S
AN3
Waiting for
conversion
ADDR0
ADDR1
ADF cleared
Simultaneous sampling
Simultaneous sampling
Stop
OFC
A/D
H
conversion
Waiting for
conversion
S
OFC
A/D
H
conversion
Waiting for
conversion
S
Waiting for
conversion
(1)
(2)
OFC
Waiting for conversion
OFC
Waiting for conversion
OFC
H
OFC
H
A/D
Waiting for
conversion conversion
S
(1)
OFC
H
Waiting for
conversion
A/D Waiting for
conversion conversion
OFC
(1)
Stop
H
A/D
conversion
Waiting for
conversion
S
Waiting for
conversion
(2)
Waiting for
conversion
A/D
conversion
Waiting for conversion
(2)
A/D conversion result (AN0)
(1)
A/D conversion result (AN0)
(2)
ADDR2
ADDR3
[Legend]
OFC: Offset canceling processing
S: Sampling
H: Holding
Note: * Instruction execution by software
A/D conversion result (AN2)
A/D conversion result (AN2)
(1)
(2)
A/D conversion result (AN3)
(1)
A/D conversion
result (AN3)
(2)
Figure 17.3 Example of A/D Converter Operation (Continuous Scan Mode)
Rev. 2.00 May. 08, 2008 Page 784 of 1200
REJ09B0344-0200