SH7211 Datasheet, PDF (26/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 1 Overview
Table 1.1 SH7211 Features
Items
CPU
Operating modes
Specification
• Renesas Technology original SuperH architecture
• Compatible with SH-1 and SH-2 at object code level
• 32-bit internal data bus
• Support of an abundant register-set
⎯ Sixteen 32-bit general registers
⎯ Four 32-bit control registers
⎯ Four 32-bit system registers
⎯ Register bank for high-speed response to interrupts
• RISC-type instruction set (upward compatible with SH series)
⎯ Instruction length: 16-bit fixed-length basic instructions for improved
code efficiency and 32-bit instructions for high performance and
usability
⎯ Load/store architecture
⎯ Delayed branch instructions
⎯ Instruction set based on C language
• Superscalar architecture to execute two instructions at one time
• Instruction execution time: Up to two instructions/cycle
• Address space: 4 Gbytes
• Internal multiplier
• Five-stage pipeline
• Operating modes
Extended ROM enabled mode
Single-chip mode
• Processing states
Program execution state
Exception handling state
Bus mastership release state
• Power-down modes
Sleep mode
Software standby mode
Module standby mode
Rev. 2.00 May. 08, 2008 Page 2 of 1200
REJ09B0344-0200