SH7211 Datasheet, PDF (1178/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
Page
10.3.3 Timer I/O
387
Control Register (TIOR)
Table 10.28 TIORU_5,
TIORV_5, and TIORW_5
(Channel 5)
10.3.20 Timer Output 421
Control Register 1
(TOCR1)
10.3.23 Timer Gate 428
Control Register (TGCR)
10.4.8 Complementary 482
PWM Mode
Figure 10.41 Example
of Operation without
Dead Time
Revision (See Manual for Details)
Table amended
Description
Bit 4
IOC4
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
1
TGRU_5,
TGRV_5, and
TGRW_5
Function
TIC5U, TIC5V, and TIC5W Pin Function
Input capture Measurement of low pulse width of external input signal
register
Capture at trough in complementary PWM mode
1
0
Measurement of low pulse width of external input signal
Capture at crest in complementary PWM mode
1
Measurement of low pulse width of external input signal
Capture at crest and trough in complementary PWM
mode
1
0
0
1
Setting prohibited
Measurement of high pulse width of external input signal
Capture at trough in complementary PWM mode
1
0
Measurement of high pulse width of external input signal
Capture at crest in complementary PWM mode
1
Measurement of high pulse width of external input signal
Capture at crest and trough in complementary PWM
mode
Notes amended
Notes: 1. This bit can be set to 1 only once after a power-on
reset. After 1 is written, 0 cannot be written to the
bit.
2. Setting the TOCL bit to 1 prevents accidental
modification when the CPU goes out of control.
3. Clearing the TOCS0 bit to 0 makes this bit setting
valid.
Note added
Initial
Bit
Bit Name Value R/W
Description
3
FB*
0
R/W
External Feedback Signal Enable
This bit selects whether the switching of the output of
the positive/reverse phase is carried out automatically
with the MTU2/channel 0 TGRA, TGRB, TGRC input
capture signals or by writing 0 or 1 to bits 2 to 0 in
TGCR.
0: Output switching is external input (Input sources are
channel 0 TGRA, TGRB, TGRC input capture signal)
1: Output switching is carried out by software (setting
values of UF, VF, and WF in TGCR).
Note: * If the BDC bit in the MTU2S is set to 1, the FB bit should not be cleared to 0.
Figure replaced
Rev. 2.00 May. 08, 2008 Page 1154 of 1200
REJ09B0344-0200