SH7211 Datasheet, PDF (1176/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
Page Revision (See Manual for Details)
8.4.2 CSn Space Bus 186
Control Register
(CSnBCR) (n = 0 to 7)
Note amended
Note: * CSnBCR samples the external pins (MD1 and MD0)
that specify the bus width at power-on reset.
8.5.6 SDRAM Interface 249
Note 3 deleted
Table 8.11 Relationship
between BSZ[1:0],
A2/3ROW[1:0],
A2/3COL[1:0], and
Address Multiplex Output
(3)-1
Table 8.11 Relationship 250
between BSZ[1:0],
A2/3ROW[1:0],
A2/3COL[1:0], and
Address Multiplex Output
(3)-2
Note 3 deleted
8.5.12 Others
295-297 Description replaced
(3) On-Chip Peripheral
Module Access
9.3.1 DMA Source
307
Address Registers (SAR)
Figure amended
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
9.3.2 DMA Destination 308
Address Registers
(DAR)
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Figure amended
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
9.3.3 DMA Transfer 309
Count Registers
(DMATCR)
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Figure amended
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 May. 08, 2008 Page 1152 of 1200
REJ09B0344-0200