SH7211 Datasheet, PDF (573/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 10.116 Timing for Status Flag Clearing by CPU (Channel 5)
Pφ, Bφ
DMAC read cycle
DMAC write cycle
Address
Source address
Destination
address
Status flag
Interrupt
request signal
Flag clear
signal
Figure 10.117 Timing for Status Flag Clearing by DTC Activation (Channels 0 to 4)
Rev. 2.00 May. 08, 2008 Page 549 of 1200
REJ09B0344-0200