SH7211 Datasheet, PDF (187/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
15
SCMFC0 0
R/W C Bus Cycle Condition Match Flag 0
When the C bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 0 does not
match
1: The C bus cycle condition for channel 0 matches
14
SCMFC1 0
R/W C Bus Cycle Condition Match Flag 1
When the C bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 1 does not
match
1: The C bus cycle condition for channel 1 matches
13
SCMFC2 0
R/W C Bus Cycle Condition Match Flag 2
When the C bus cycle condition in the break conditions
set for channel 2 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 2 does not
match
1: The C bus cycle condition for channel 2 matches
12
SCMFC3 0
R/W C Bus Cycle Condition Match Flag 3
When the C bus cycle condition in the break conditions
set for channel 3 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 3 does not
match
1: The C bus cycle condition for channel 3 matches
11
SCMFD0 0
R/W I Bus Cycle Condition Match Flag 0
When the I bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 0 does not
match
1: The I bus cycle condition for channel 0 matches
Rev. 2.00 May. 08, 2008 Page 163 of 1200
REJ09B0344-0200