SH7211 Datasheet, PDF (1145/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 27 Electrical Characteristics
CK
A25 to A0
A12/A11^*1
Tp
Tpw
Trr
Trc
Trc
t_AD1
t_AD1
t_AD1
t_AD1
CSn
RD/WR
RASL
CASL
t_CSD1
t_CSD1
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
Trc
t_RWD1
DQMLx
D15 to D0
(Hi-Z)
BS
CKE
(High)
DACKn
TENDn*²
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 27.34 Synchronous DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles)
Rev. 2.00 May. 08, 2008 Page 1121 of 1200
REJ09B0344-0200