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SH7211 Datasheet, PDF (661/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family | |||
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Section 13 Compare Match Timer (CMT)
Section 13 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer.
The CMT has a16-bit counter, and can generate interrupts at set intervals.
13.1 Features
⢠Independent selection of four counter input clocks at two channels
Any of four internal clocks (PÏ/8, PÏ/32, PÏ/128, and PÏ/512) can be selected.
⢠Selection of DMA transfer request or interrupt request generation on compare match by
DMAC setting
⢠When not in use, the CMT can be stopped by halting its clock supply to reduce power
consumption.
Figure 13.1 shows a block diagram of CMT.
CMI0
PÏ/8 PÏ/32 PÏ/128 PÏ/512
CMI1
PÏ/8 PÏ/32 PÏ/128 PÏ/512
Control circuit
Clock selection
Control circuit
Clock selection
Channel 0
Module bus
CMT
[Legend]
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCOR: Compare match constant register
CMCNT: Compare match counter
CMI:
Compare match interrupt
Figure 13.1 Block Diagram of CMT
Channel 1
Bus
interface
Internal bus
Rev. 2.00 May. 08, 2008 Page 637 of 1200
REJ09B0344-0200
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