SH7211 Datasheet, PDF (194/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 7 User Break Controller (UBC)
7.4.5 Usage Examples
(1) Break Condition Specified for C Bus Instruction Fetch Cycle
(Example 1-1)
• Register specifications
BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010,
BAMR_1 = H'00000006, BBR_1 = H'0054, BRCR = H'00000020
<Channel 0>
Address: H'00000404, Address mask: H'00000000
Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
<Channel 1>
Address: H'00008010, Address mask: H'00000006
Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of addresses H'00008010 to H'00008016 are executed.
(Example 1-2)
• Register specifications
BAR_0 = H'00027128, BAMR_0 = H'00000000, BBR_0 = H'005A, BAR_1= H'00031415,
BAMR_1 = H'00000000, BBR_1 = H'0054, BRCR = H'00000000
<Channel 0>
Address: H'00027128, Address mask: H'00000000
Bus cycle: C bus/instruction fetch (before instruction execution)/write/word
<Channel 1>
Address: H'00031415, Address mask: H'00000000
Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
On channel 0, a user break does not occur since instruction fetch is not a write cycle. On
channel 1, a user break does not occur since instruction fetch is performed for an even address.
Rev. 2.00 May. 08, 2008 Page 170 of 1200
REJ09B0344-0200