SH7211 Datasheet, PDF (1175/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
Page
6.5 Interrupt Exception 119
Handling Vector Table
and Priority
Table 6.4 Interrupt
Exception Handling
Vectors and Priorities
6.7 Interrupt Response 130
Time
Table 6.5 Interrupt
Response Time
8.1 Features
177
Figure 8.1 Block
Diagram of BSC
8.3.2 Setting Operating 181
Modes
Revision (See Manual for Details)
Table amended
Interrupt Source Number
DMAC DMAC0 DEI0
HEI0
DMAC1 DEI1
HEI1
DMAC2 DEI2
HEI2
DMAC3 DEI3
HEI3
DMAC4 DEI4
HEI4
DMAC5 DEI5
HEI5
DMAC6 DEI6
HEI6
DMAC7 DEI7
HEI7
Notes amended
Notes: 2. In the case that (Iφ, Bφ, Pφ) = (160 MHz, 40 MHz,
40 MHz).
Description amended
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0 to 7)
CSnBCR: CSn space bus control register (n = 0 to 7)
Description amended
• Initial Settings of Endianness
… In on-chip ROM-enabled mode, all the endianness of
areas 0 to 7 can be changed by register settings in the
program. Little endian cannot be selected in area 0. Since
both 32-bit and 16-bit accesses are included in instruction
fetches, no instructions can be assigned in little endian
area. Accordingly, instructions should be executed in big
endian area.
Rev. 2.00 May. 08, 2008 Page 1151 of 1200
REJ09B0344-0200