 English |
|
|
|
|
|
|
|
| SH7211 Datasheet, PDF (298/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family | |||
| |||
| ◁ |
Section 8 Bus State Controller (BSC)
Tp
Tpw
Trr
Trc
PALL
REF
CK
Trc
Trr
Trc
REF
Trc Tmw Tnop
MRS
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
Hi-Z
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 8.29 SDRAM Mode Write Timing (Based on JEDEC)
Rev. 2.00 May. 08, 2008 Page 274 of 1200
REJ09B0344-0200
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese