SH7211 Datasheet, PDF (417/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
• TIER_5
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
- TGIE5U TGIE5V TGIE5W
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 3 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
TGIE5U
0
R/W TGR Interrupt Enable 5U
Enables or disables interrupt requests (TGIU_5) by the
CMFU5 bit when this bit in TSR_5 is set to 1.
0: Interrupt requests (TGIU_5) disabled
1: Interrupt requests (TGIU_5) enabled
1
TGIE5V
0
R/W TGR Interrupt Enable 5V
Enables or disables interrupt requests (TGIV_5) by the
CMFV5 bit when this bit in TSR_5 is set to 1.
0: Interrupt requests (TGIV_5) disabled
1: Interrupt requests (TGIV_5) enabled
0
TGIE5W 0
R/W TGR Interrupt Enable 5W
Enables or disables interrupt requests (TGIW_5) by the
CMFW5 bit when this bit in TSR_5 is set to 1.
0: Interrupt requests (TGIW_5) disabled
1: Interrupt requests (TGIW_5) enabled
Rev. 2.00 May. 08, 2008 Page 393 of 1200
REJ09B0344-0200