SH7211 Datasheet, PDF (130/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
Register Name
Interrupt priority
register 13
Interrupt priority
register 14
Interrupt priority
register 15
Bits 15 to 12
MTU5S
(TGI5U, TGI5V,
TGI5W)
SCIF0
WAVEIF
Bits 11 to 8
POE2
(OEI3)
SCIF1
Reserved
Bits 7 to 4
IIC3
SCIF2
Reserved
Bits 3 to 0
Reserved
SCIF3
Reserved
As shown in table 6.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3
to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set.
Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the
highest level).
IPR01, IPR02, and IPR05 to IPR15 are initialized to H'0000 by a power-on reset.
Rev. 2.00 May. 08, 2008 Page 106 of 1200
REJ09B0344-0200