SH7211 Datasheet, PDF (933/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
Bit
31 to
16
Bit Name
⎯
Initial
Value
R/W
Undefined R/W
15 to 0 F15 to F0 Undefined R/W
Description
Unused
Return 0.
Frequency Set
Set the operating frequency Iφ of the CPU following the
calculation below.
Iφ = F[15:0] × 10⁴ Hz
1. Round it off to the digit of 1 kHz, and round down the
lower digits.
2. For example, when Iφ = 33.333 MHz, set as follows:
(1) Iφ = 3333 × 10⁴ Hz
(2) F[15:0] = 3333 (H'0D05)
(3) Set R4 (FPEFEQ) to H'00000D05.
(2.2) Flash User Branch Address Setting Parameter (FUBRA: General Register R5 of CPU)
This parameter sets the user branch destination address. The user program which has been set can
be executed in specified processing units when programming and erasing.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UA31 UA30 UA29 UA28 UA27 UA26 UA25 UA24 UA23 UA22 UA21 UA20 UA19 UA18 UA17 UA16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
UA15
Initial value: -
R/W: R/W
14
UA14
-
R/W
13
UA13
-
R/W
12
UA12
-
R/W
11
UA11
-
R/W
10
UA10
-
R/W
9
UA9
-
R/W
8
UA8
-
R/W
7
UA7
-
R/W
6
UA6
-
R/W
5
UA5
-
R/W
4
UA4
-
R/W
3
UA3
-
R/W
2
UA2
-
R/W
1
UA1
-
R/W
0
UA0
-
R/W
Rev. 2.00 May. 08, 2008 Page 909 of 1200
REJ09B0344-0200