SH7211 Datasheet, PDF (788/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 16 I²C Bus Interface 3 (IIC3)
16.6 Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 16.22 shows the timing of the bit synchronous circuit and table 16.5 shows the time when
the SCL output changes from low to Hi-Z then SCL is monitored.
Rev. 2.00 May. 08, 2008 Page 764 of 1200
REJ09B0344-0200