SH7211 Datasheet, PDF (689/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 15 Serial Communication Interface with FIFO (SCIF)
Section 15 Serial Communication Interface with FIFO
(SCIF)
This LSI has a four-channel serial communication interface with FIFO (SCIF) that supports both
asynchronous and clocked synchronous serial communication. It also has 16-stage FIFO registers
for both transmission and reception independently for each channel that enable this LSI to perform
efficient high-speed continuous communication.
15.1 Features
• Asynchronous serial communication:
⎯ Serial data communication is performed by start-stop in character units. The SCIF can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
⎯ Data length: 7 or 8 bits
⎯ Stop bit length: 1 or 2 bits
⎯ Parity: Even, odd, or none
⎯ Receive error detection: Parity, framing, and overrun errors
⎯ Break detection: Break is detected when a framing error is followed by at least one frame at
the space 0 level (low level). It is also detected by reading the RXD level directly from the
serial port register when a framing error occurs.
• Clocked synchronous serial communication:
⎯ Serial data communication is synchronized with a clock signal. The SCIF can communicate
with other chips having a clocked synchronous communication function. There is one serial
data communication format.
⎯ Data length: 8 bits
⎯ Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the
SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so
high-speed continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
Rev. 2.00 May. 08, 2008 Page 665 of 1200
REJ09B0344-0200