SH7211 Datasheet, PDF (525/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
(o) Suppressing MTU2–MTU2S Synchronous Counter Clearing
In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing caused
by the MTU2.
Synchronous counter clearing is suppressed only within the interval shown in figure 10.62. When
using this function, the MTU2S should be set to complementary PWM mode.
For details of synchronous clearing caused by the MTU2, refer to the description about MTU2S
counter clearing caused by MTU2 flag setting source (MTU2-MTU2S synchronous counter
clearing) in section 10.4.10, MTU2–MTU2S Synchronous Operation.
Tb interval
immediately
after counter
operation starts
Tb interval
at the crest
TGRA_3
TCDR
TGRB_3
Tb interval
at the trough
Tb interval
at the crest
Tb interval
at the trough
TDDR
H'0000
MTU2-MTU2S synchronous counter
clearing is suppressed.
MTU2-MTU2S synchronous counter
clearing is suppressed.
Figure 10.62 MTU2–MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC
Bit in TWCR
Rev. 2.00 May. 08, 2008 Page 501 of 1200
REJ09B0344-0200