SH7211 Datasheet, PDF (970/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
(2) Interrupts during Programming/Erasing
Though an interrupt processing can be executed at realtime during programming/erasing of the
downloaded on-chip program, the following limitations and notes are applied.
1. When flash memory is being programmed or erased, both the user MAT and user boot
MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing
routine in on-chip RAM or external memory. Make sure the flash memory being
programmed or erased is not accessed by the interrupt processing routine. If flash memory
is read, the read values are not guaranteed. If the relevant bank in flash memory that is
being programmed or erased is accessed, the error protection state is entered, and
programming or erasing is aborted. If a bank other than the relevant bank is accessed, the
error protection state is not entered but the read values are not guaranteed.
2. Do not rewrite the program data specified by the FMPDR parameter. If new program data
is to provided by the interrupt processing, temporarily save the new program data in
another area. After confirming the completion of programming, save the new program data
in the area specified by FMPDR or change the setting in FMPDR to indicated the other
area in which the new program data was temporarily saved.
3. Make sure the interrupt processing routine does not rewrite the contents of the flash-
memory related registers or data in the downloaded on-chip program area. During the
interrupt processing, do not simultaneously perform download of the on-chip program by
an SCO request or programming/erasing.
4. At the beginning of the interrupt processing routine, save the CPU register contents. Before
returning from the interrupt processing, write the saved contents in the CPU registers again.
5. When a transition is made to sleep mode or software standby mode in the interrupt
processing routine, the error protection state is entered and programming/erasing is
aborted.
If a transition is made to the reset state, the reset signal should only be released after
providing a reset input over a period longer than the normal 100 μs to reduce the damage to
flash memory.
21.7.3 Other Notes
(1) Download Time of On-Chip Program
The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 3 kbytes or less. Accordingly, when the CPU clock
frequency is 40 MHz, the download for each program takes approximately 10 ms at maximum.
Rev. 2.00 May. 08, 2008 Page 946 of 1200
REJ09B0344-0200