SH7211 Datasheet, PDF (713/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.4 Bit Rates and SCBRR Settings (Asynchronous Mode)
Pφ (MHz)
32
36
Bit Rate (bit/s) n N
Error (%) n
N
Error (%) n
110
3 141 0.03
3
159 –0.12 3
150
3 103 0.16
3
116 0.16
3
300
3 51
0.16
3
58
–0.69 3
600
2 103 0.16
2
116 0.16
2
1200
2 51
0.16
2
58
–0.69 2
2400
1 103 0.16
1
116 0.16
1
4800
1 51
0.16
1
58
–0.69 1
9600
0 103 0.16
0
116 0.16
0
19200
0 51
0.16
0
58
–0.69 0
31250
0 31
0.00
0
35
0.00
0
38400
0 25
0.16
0
28
1.02
0
Note: Settings with an error of 1% or less are recommended.
40
N
Error (%)
117 –0.25
129 0.16
64 0.16
129 0.16
64 0.16
129 0.16
64 0.16
129 0.16
64 0.16
39 0.00
32 –1.36
Rev. 2.00 May. 08, 2008 Page 689 of 1200
REJ09B0344-0200