SH7211 Datasheet, PDF (772/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 16 I²C Bus Interface 3 (IIC3)
Master transmit mode
SCL
(Master output)
9
SDA
(Master output)
SDA
(Slave output)
A
TDRE
TEND
TRS
Master receive mode
1
2
3
4
5
6
7
8
9
1
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
RDRF
ICDRS
Data 1
ICDRR
User
[1] Clear TDRE after clearing [2] Read ICDRR (dummy read)
processing
TEND and TRS
Data 1
[3] Read ICDRR
Figure 16.7 Master Receive Mode Operation Timing (1)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
RDRF
RCVD
9
1
2
3
4
5
6
7
8
9
A
A/A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRS Data n-1
Data n
ICDRR
User
processing
Data n-1
Data n
[5] Read ICDRR after setting RCVD
[6] Issue stop
condition
[7] Read ICDRR,
and clear RCVD
Figure 16.8 Master Receive Mode Operation Timing (2)
[8] Set slave
receive mode
Rev. 2.00 May. 08, 2008 Page 748 of 1200
REJ09B0344-0200