SH7211 Datasheet, PDF (322/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
8.6 Usage Notes
8.6.1 Burst ROM Interface
When the burst ROM interface (clock asynchronous) is used and the following three conditions
are met, read/write access from the external bus space immediately after write access may be
invalid.
1. The 16-bit bus width is used for the burst ROM interface (clock asynchronous). (The
CSnBCR.TYPE[2:0] setting is B'001 and the CSnWCR.BSZ[1:0] setting is B'10)
2. The burst length is specified as 4. (The CSnWCR.BST[1:0] setting is B'10)
3. Write-back is performed with operand cache or 16-byte write access is performed with the
DMAC for the burst ROM interface set as above.
Rev. 2.00 May. 08, 2008 Page 298 of 1200
REJ09B0344-0200