SH7211 Datasheet, PDF (132/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
6.3.3 Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to
IRQ0 individually: low level, falling edge, rising edge, or both edges. ICR1 is initialized by a
power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15
IRQ71S
14
IRQ70S
13
IRQ61S
12
IRQ60S
11
IRQ51S
10
IRQ50S
9
IRQ41S
8
IRQ40S
7
IRQ31S
6
IRQ30S
5
IRQ21S
4
IRQ20S
3
IRQ11S
2
IRQ10S
1
IRQ01S
0
IRQ00S
[Legend]
n = 7 to 0
Initial
Value R/W Description
0
R/W IRQ Sense Select
0
R/W These bits select whether interrupt signals
0
R/W
corresponding to pins IRQ7 to IRQ0 are detected by a
low level, falling edge, rising edge, or both edges.
0
R/W _{00: Interrupt request is detected on low level of IRQn}
0
R/W
input
0
R/W 01: Interrupt request is detected on falling edge of IRQn
0
R/W
input
0
R/W ^{10: Interrupt request is detected on rising edge of IRQn}
input
0
R/W _{11: Interrupt request is detected on both edges of IRQn}
0
R/W
input
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Rev. 2.00 May. 08, 2008 Page 108 of 1200
REJ09B0344-0200