SH7211 Datasheet, PDF (676/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 14 Watchdog Timer (WDT)
14.3 Register Descriptions
The WDT has the following registers.
Table 14.2 Register Configuration
Register Name
Abbreviation R/W
Initial
Value
Address
Watchdog timer counter
WTCNT
R/W H'00
H'FFFE0002
Watchdog timer control/status
register
WTCSR
R/W H'18
H'FFFE0000
Watchdog reset control/status
register
WRCSR
R/W H'1F
H'FFFE0004
Note: * For the access size, see section 14.3.4, Notes on Register Access.
Access
Size
16*
16*
16*
14.3.1 Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock
signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in
watchdog timer mode and an interrupt in interval timer mode. WTCNT is initialized to H'00 by a
power-on reset caused by the RES pin or in software standby mode.
Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read
from WTCNT.
Note: The method for writing to WTCNT differs from that for other registers to prevent
erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 May. 08, 2008 Page 652 of 1200
REJ09B0344-0200