SH7211 Datasheet, PDF (152/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
6.6.2 Stack after Interrupt Exception Handling
Figure 6.3 shows the stack after interrupt exception handling.
Address
4n – 8 PC*¹
4n – 4 SR
4n
32 bits
32 bits
SP*²
Notes: 1. PC: Start address of the next instruction (return destination instruction)
after the executed instruction
2. Always make sure that SP is a multiple of 4.
Figure 6.3 Stack after Interrupt Exception Handling
Rev. 2.00 May. 08, 2008 Page 128 of 1200
REJ09B0344-0200