SH7211 Datasheet, PDF (86/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 4 Clock Pulse Generator (CPG)
On-chip oscillator
PLL circuit 1
(×1, 2, 4)
Divider 1
×1
×1/2
×1/4
×1/8
CK
XTAL
EXTAL
Crystal
oscillator
PLL circuit 2
(×4)
Internal clock
(Iφ, Max. 160 MHz)
Bus clock
(Bφ = CK, Max. 40 MHz)
Peripheral clock
(Pφ, Max. 40 MHz)
MTU2S clock
(Mφ, Max. 80 MHz)
AD clock
(Aφ, Max. 40 MHz)
MD_CLK2
MD_CLK0
CPG control unit
Clock frequency
control circuit
Standby control circuit
FRQCR MCLKCR ACLKCR STBCR STBCR2 STBCR3 STBCR4
Bus interface
[Legend]
FRQCR: Frequency control register
MCLKCR: MTU2S clock frequency control register
ACLKCR: AD clock frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
STBCR3: Standby control register 3
STBCR4: Standby control register 4
HPB bus
Figure 4.1 Block Diagram of Clock Pulse Generator
Rev. 2.00 May. 08, 2008 Page 62 of 1200
REJ09B0344-0200