SH7211 Datasheet, PDF (682/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 14 Watchdog Timer (WDT)
14.4 WDT Usage
14.4.1 Canceling Software Standby Mode
The WDT can be used to cancel software standby mode with an interrupt such as an NMI
interrupt. The procedure is described below. (The WDT does not operate when resets are used for
canceling, so keep the RES or MRES pin low until clock oscillation settles.)
1. Before making a transition to software standby mode, always clear the TME bit in WTCSR
to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated
when the count overflows.
2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the
counter in WTCNT. These values should ensure that the time till count overflow is longer than
the clock oscillation settling time.
3. After setting the STBY bit of the standby control register (STBCR: see section 23, Power-
Down Modes) to 1, the execution of a SLEEP instruction puts the system in software standby
mode and clock operation then stops.
4. The WDT starts counting by detecting the edge change of the NMI signal.
5. When the WDT count overflows, the CPG starts supplying the clock and this LSI resumes
operation. The WOVF flag in WRCSR is not set when this happens.
Rev. 2.00 May. 08, 2008 Page 658 of 1200
REJ09B0344-0200