SH7211 Datasheet, PDF (1190/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
Page
21.4.3 Programming/ 914
Erasing Interface
Parameters
(3) Programming
Execution
(3.3) Flash Pass/Fail
Result Parameter
(FPFR: General Register
R0 of CPU)
21.5.2 User Program 926
Mode
(2) Programming
Procedure in User
Program Mode
Figure 21.11
Programming Procedure
(3) Erasing Procedure 932
in User Program Mode
Figure 21.12 Erasing
Procedure
933
Revision (See Manual for Details)
Title amended
Figure amended
Start programming
procedure program
Set internal clock ratio by
frequency control register
(FRQCR) to 4: 4: 4
Description amended
… Specify 4:4:4 as the frequency division ratios of an
internal clock (Iφ), a bus clock (Bφ), and a peripheral clock
(Pφ) through the frequency control register (FRQCR).
Figure amended
Start erasing procedure
program
Set internal clock ratio by
frequency control register
(FRQCR) to 4:4:4
Description amended
The frequency division ratio of an internal clock (Iφ), a bus
clock (Bφ), and a peripheral clock (Pφ) is specified as 4:4:4
by the frequency control register (FRQCR).
Rev. 2.00 May. 08, 2008 Page 1166 of 1200
REJ09B0344-0200