SH7211 Datasheet, PDF (1217/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Index
Numerics
16-bit/32-bit displacement ........................ 25
A
A/D conversion time............................... 786
A/D converter (ADC) ............................. 769
A/D converter activation......................... 536
A/D converter activation
by MTU2 and MTU2S............................ 787
A/D converter start request delaying
function................................................... 518
Absolute accuracy................................... 791
Absolute address....................................... 25
Absolute address accessing....................... 25
Access size and data alignment .............. 229
Access wait control................................. 236
Address errors........................................... 87
Address map ........................................... 179
Address multiplexing.............................. 244
Addressing modes..................................... 26
Arithmetic operation instructions ............. 44
Auto-refreshing....................................... 265
Auto-request mode.................................. 329
B
Bank active ............................................. 258
Banked register and input/output
of banks .................................................. 136
Bit manipulation instructions.................... 52
Bit synchronous circuit ........................... 764
Block diagram............................................. 7
Boot mode............................................... 920
Branch instructions ................................... 49
Break detection and processing .............. 722
Break on data access cycle...................... 168
Break on instruction fetch cycle.............. 167
Burst mode .............................................. 342
Burst read ................................................ 251
Burst ROM (clock asynchronous)
interface .................................................. 278
Burst ROM (clock synchronous)
interface .................................................. 285
Burst write............................................... 255
Bus arbitration......................................... 293
Bus state controller (BSC) ...................... 175
Bus-released state...................................... 54
C
Calculating exception handling
vector table addresses................................ 82
Canceling software standby mode
(WDT)..................................................... 658
Cascaded operation ................................. 452
Caution on period setting ........................ 551
Changing the division ratio ....................... 74
Changing the frequency .................... 73, 659
Changing the multiplication rate............... 73
Clock frequency control circuit................. 63
Clock operating modes.............................. 66
Clock pulse generator (CPG) .................... 61
Clocked synchronous serial format ......... 754
CMCNT count timing ............................. 643
Compare match timer (CMT) ................. 637
Complementary PWM mode .................. 472
Conditions for determining number
of idle cycles ........................................... 287
Conflict between byte-write
and count-up processes of CMCNT ........ 648
Conflict between word-write
and count-up processes of CMCNT ........ 647
Rev. 2.00 May. 08, 2008 Page 1193 of 1200
REJ09B0344-0200