SH7211 Datasheet, PDF (63/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 2 CPU
The table below shows the format of instruction codes, operation, and execution states. They are
described by using this format according to their classification.
Instruction
Instruction Code Operation
Execution
States
T Bit
Indicated by mnemonic.
Indicated in MSB ↔
LSB order.
Indicates summary of
operation.
Value when no
wait states are
inserted.*¹
Value of T bit after
instruction is
executed.
[Legend]
[Legend]
[Legend]
Explanation of
Symbols
OP.Sz SRC, DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*²
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
.........
1111: R15
iiii: Immediate data
dddd: Displacement
→, ←: Transfer direction
(xx): Memory operand
M/Q/T: Flag bits in SR
&: Logical AND of each bit
|: Logical OR of each bit
^: Exclusive logical OR of
each bit
~: Logical NOT of each bit
<<n: n-bit left shift
—: No change
>>n: n-bit right shift
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In
practice, the number of instruction execution states will be increased in cases such as
the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory → register) is the same
as the register used by the next instruction.
2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details,
refer to the SH-2A, SH2A-FPU Software Manual.
Rev. 2.00 May. 08, 2008 Page 39 of 1200
REJ09B0344-0200