SH7211 Datasheet, PDF (10/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

3.3.1 Mode 0 (MCU Extension Mode 0) ......................................................................... 57
3.3.2 Mode 1 (MCU Extension Mode 1) ......................................................................... 57
3.3.3 Mode 2 (MCU Extension Mode 2) ......................................................................... 57
3.3.4 Mode 3 (Single Chip Mode) ................................................................................... 57
3.4 Address Map ........................................................................................................................ 58
3.5 Initial State in This LSI........................................................................................................ 59
3.6 Note on Changing Operating Mode ..................................................................................... 59
Section 4 Clock Pulse Generator (CPG) ...............................................................61
4.1 Features................................................................................................................................ 61
4.2 Input/Output Pins................................................................................................................. 65
4.3 Clock Operating Modes ....................................................................................................... 66
4.4 Register Descriptions ........................................................................................................... 68
4.4.1 Frequency Control Register (FRQCR) ................................................................... 68
4.4.2 MTU2S Clock Frequency Control Register (MCLKCR) ....................................... 71
4.4.3 AD Clock Frequency Control Register (ACLKCR) ............................................... 72
4.5 Changing the Frequency ...................................................................................................... 73
4.5.1 Changing the Multiplication Rate........................................................................... 73
4.5.2 Changing the Division Ratio................................................................................... 74
4.6 Notes on Board Design ........................................................................................................ 75
4.6.1 Note on Using an External Crystal Resonator ........................................................ 75
4.6.2 Note on Bypass Capacitor....................................................................................... 75
4.6.3 Note on Using a PLL Oscillation Circuit................................................................ 75
Section 5 Exception Handling ............................................................................... 77
5.1 Overview.............................................................................................................................. 77
5.1.1 Types of Exception Handling and Priority ............................................................. 77
5.1.2 Exception Handling Operations.............................................................................. 79
5.1.3 Exception Handling Vector Table .......................................................................... 81
5.2 Resets................................................................................................................................... 83
5.2.1 Types of Reset ........................................................................................................ 83
5.2.2 Power-On Reset ...................................................................................................... 84
5.2.3 Manual Reset .......................................................................................................... 86
5.3 Address Errors ..................................................................................................................... 87
5.3.1 Address Error Sources ............................................................................................ 87
5.3.2 Address Error Exception Handling ......................................................................... 88
5.4 Register Bank Errors............................................................................................................ 89
5.4.1 Register Bank Error Sources................................................................................... 89
5.4.2 Register Bank Error Exception Handling ............................................................... 89
5.5 Interrupts.............................................................................................................................. 90
Rev. 2.00 May. 08, 2008 Page x of xxiv
REJ09B0344-0200