EFM32WG Datasheet, PDF (99/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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up. At startup the EFM32WG loads the stack pointer and program entry point from memory, and starts
execution.
As seen in Figure 9.1 (p. 99) the Power-on Reset, Brown-out Detectors, Watchdog timeout and
RESETn pin all reset the whole system including the Debug Interface. A Core Lockup condition or a
System reset request from software resets the whole system except the Debug Interface.
Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set. At
startup the program code may investigate this register in order to determine the cause of the reset. The
register must be cleared by software.
Figure 9.1. RMU Reset Input Sources and Connections.
POR
VDD
BOD
VDD_REGULATED _BOD
AVDD0
BOD
AVDD1
RESETn
BOD
Filt er
Reset Managem ent Unit
POWERONn
BROWNOUT_UNREGn
BROWNOUT_REGn
BROWNOUT_AVDD0
BROWNOUT_AVDD1
EM4 wakeup
Backup m ode exit
WDOG
em 4
Backup m ode
RCCLR
LOCKUP
LOCKUPRDIS
RMU_RSTCAUSE
Edge-t o-pulse
filter
SYSREQRST
PORESETn
SYSRESETn
Cort ex
Debug
In t er f ace
Co r e
Pe r i p h e r a l s
9.3.1 RMU_RSTCAUSE Register
The RMU_RSTCAUSE register indicates the reason for the last reset. The register should be cleared
after the value has been read at startup. Otherwise the register may indicate multiple causes for the
reset at next startup.
The following procedure must be done to clear RMU_RSTCAUSE:
1. Write a 1 to RCCLR in RMU_CMD
2. Write a 1 to bit 0 in EMU_AUXCTRL
3. Write a 0 to bit 0 in EMU_AUXCTRL
RMU_RSTCAUSE should be interpreted according to Table 9.1 (p. 100) . X bits are don't care. Notice
that it is possible to have multiple reset causes. For example, an external reset and a watchdog reset
may happen simultaneously.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
99
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