EFM32WG Datasheet, PDF (828/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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26.2. 20 mV Hysteresis Selected .................................................................................................................. 664
26.3. Capacitive Sensing Set-up ................................................................................................................... 665
27.1. VCMP Overview ................................................................................................................................ 673
27.2. VCMP 20 mV Hysteresis Enabled ......................................................................................................... 674
28.1. ADC Overview .................................................................................................................................. 682
28.2. ADC Conversion Timing ...................................................................................................................... 683
28.3. ADC Analog Power Consumption With Different WARMUPMODE Settings .................................................... 684
28.4. ADC RC Input Filter Configuration ........................................................................................................ 684
28.5. ADC Bias Programming ...................................................................................................................... 686
28.6. ADC Conversion Tailgating .................................................................................................................. 687
29.1. DAC Overview .................................................................................................................................. 705
29.2. DAC Bias Programming ...................................................................................................................... 707
29.3. DAC Sine Mode ................................................................................................................................ 708
30.1. OPAMP System Overview ................................................................................................................... 726
30.2. OPAMP Overview .............................................................................................................................. 727
30.3. Opamp Output Stage Overview ............................................................................................................ 728
30.4. Voltage Follower Unity Gain Overview ................................................................................................... 729
30.5. Inverting input PGA Overview .............................................................................................................. 730
30.6. Non-inverting PGA Overview ................................................................................................................ 730
30.7. Cascaded Inverting PGA Overview ....................................................................................................... 731
30.8. Cascaded Non-inverting PGA Overview ................................................................................................. 731
30.9. Two Op-amp Differential Amplifier Overview ........................................................................................... 733
30.10. Three Op-amp Differential Amplifier Overview ........................................................................................ 734
30.11. Dual Buffer ADC Driver Overview ....................................................................................................... 735
31.1. AES Key and Data Definitions .............................................................................................................. 737
31.2. AES Data and Key Orientation as Defined in the Advanced Encryption Standard ............................................ 737
31.3. AES Data and Key Register Operation .................................................................................................. 738
32.1. Pin Configuration ............................................................................................................................... 750
32.2. Tristated Output with Optional Pull-up or Pull-down .................................................................................. 751
32.3. Push-Pull Configuration ....................................................................................................................... 752
32.4. Open-drain ....................................................................................................................................... 752
32.5. EM4 Wake-up Logic ........................................................................................................................... 753
32.6. Pin n Interrupt Generation ................................................................................................................... 754
33.1. LCD Block Diagram ........................................................................................................................... 775
33.2. LCD Low-power Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias ........................................ 777
33.3. LCD Normal Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias ............................................ 777
33.4. LCD Static Bias and Multiplexing - LCD_COM0 ....................................................................................... 777
33.5. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM0 ................................................................................ 778
33.6. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM1 ................................................................................ 778
33.7. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 ................................................................................. 778
33.8. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 Connection ................................................................. 778
33.9. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 ................................................................ 779
33.10. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 779
33.11. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM0 .............................................................................. 779
33.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1 .............................................................................. 779
33.13. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 ............................................................................... 780
33.14. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 Connection ............................................................... 780
33.15. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 .............................................................. 780
33.16. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 781
33.17. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM0 ............................................................................... 781
33.18. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM1 ............................................................................... 781
33.19. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM2 ............................................................................... 781
33.20. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 ............................................................................... 782
33.21. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 Connection ................................................................ 782
33.22. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 .............................................................. 782
33.23. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 782
33.24. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2 .............................................................. 783
33.25. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM0 ............................................................................... 783
33.26. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM1 ............................................................................... 783
33.27. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM2 ............................................................................... 783
33.28. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0 ............................................................................... 784
33.29. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0 Connection ................................................................ 784
33.30. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 .............................................................. 784
33.31. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 784
33.32. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2 .............................................................. 785
33.33. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM0 ........................................................................ 785
33.34. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM1 ........................................................................ 785
33.35. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM2 ........................................................................ 785
33.36. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM3 ........................................................................ 786
33.37. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 ......................................................................... 786
33.38. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 Connection ......................................................... 786
33.39. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM0 ........................................................ 786
33.40. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM1 ........................................................ 787
33.41. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM2 ........................................................ 787
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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